The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method suitably adapted for forming an isolation region between a well region and a semiconductor substrate of a complementary semiconductor device.
Some semiconductor devices have two types of transistors having different polarities on a single semiconductor substrate. For example, a CMOS (Complementary MOS) among various MOS (Metal Oxide Semiconductor) devices has a p-channel transistor and an n-channel transistor. A bipolar transistor among various bipolar devices has an npn transistor and a pnp transistor. In a semiconductor device of this type, if one of the transistors is formed within the semiconductor substrate, the other is formed in an impurity region (generally a well region) of the opposite conductivity type in the semiconductor substrate. The transistors are isolated at the boundary between the well region and the semiconductor substrate. However, in a CMOS transistor, for example, since the p- and n-channel transistors are present on a single semiconductor substrate, defective modes are caused such as the turn-on phenomenon of a parasitic thyristor (so-called latch-up phenomenon) or various breakdown phenomena. In order to prevent such defective modes, possible reduction in the clearance between the p- and n-channel transistors is greatly limited. As a result of this, the clearance margin must be made relatively large.
In order to reduce the clearance between the p- and n-channel transistors without causing the defective modes as described above, the formation of an insulating film in the boundary region between both transistors is known to be effective.
A conventional method for forming such an insulating film (element isolation region) typically comprises the step of ion-implanting an impurity of the opposite conductivity type to that of a semiconductor substrate into a desired region thereof by the photoetching process (PEP), and diffusing the ion-implanted impurity by annealing to a predetermined depth (e.g., 5 .mu.m), thereby forming a well region in the semiconductor substrate; and forming an insulating film in a boundary region between the well region and the semiconductor substrate by PEP again.
However, in this conventional method, two PEP steps are required so that mask misalignment (e.g., 0.5 .mu.m) which might occur during the two PEP steps must be considered. This impairs micronization and requires one to determine, in advance, the lateral diffusion of the impurity (well region).